The background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
The physical product of any design will vary from an idealized design due to imperfect manufacturing conditions. The competitive world of microchip design requires that design engineers test new designs having inherent construction variations quickly and accurately. Design engineers can test microchip designs using a design-of-experiments (DOE) technique by simulating a new design with process corners that represent the extreme attributes when parameters vary. Fully exhaustive simulations using all process corners are highly accurate but may take days to run, whereas simulations using only a few process corners take only minutes to run, but may not detect the best and worst-case scenarios.
Simplistic FEOL (Front End of Line) traditional corners can be chosen by simulating a circuit where the NMOS and PMOS transistors have no variation (referred to as typical), when they are at their fastest, and when they are at their slowest, which would provide five corners to test (i.e. typical, fast-fast, fast-slow, slow-fast, and slow-slow). However, traditional FEOL corners are overly simplistic, and frequently represent impossible worst-case scenarios.
A design engineer might perform simulations that sweep through a range of values at predetermined intervals across corners, but randomized techniques require many repeated iterations to provide accuracy which wastes time. Relationships between performance targets and statistical model parameters could be used to strategically choose corner models, however it is difficult to derive statistical model parameters that would provide accurate worse-case scenarios.
Thus, there remains a need for a system and method that derives and tests process corners specifically for different design analysis.